publications

2023

1. Hardware Trojan Detection Using Machine Learning: A Tutorial

   Kevin Immanuel Gubbi, Banafsheh Saber Latibari, Anirudh Srikanth, and 7 more authors

   ACM Trans. Embed. Comput. Syst., Apr 2023

   Abs

   With the growth and globalization of IC design and development, there is an increase in the number of Designers and Design houses. As setting up a fabrication facility may easily cost upwards of $20 billion, costs for advanced nodes may be even greater. IC design houses that cannot produce their chips in-house have no option but to use external foundries that are often in other countries. Establishing trust with these external foundries can be a challenge, and these foundries are assumed to be untrusted. The use of these untrusted foundries in the global semiconductor supply chain has raised concerns about the security of the fabricated ICs targeted for sensitive applications. One of these security threats is the adversarial infestation of fabricated ICs with a Hardware Trojan (HT). An HT can be broadly described as a malicious modification to a circuit to control, modify, disable, or monitor its logic. Conventional VLSI manufacturing tests and verification methods fail to detect HT due to the different and un-modeled nature of these malicious modifications. Current state-of-the-art HT detection methods utilize statistical analysis of various side-channel information collected from ICs, such as power analysis, power supply transient analysis, regional supply current analysis, temperature analysis, wireless transmission power analysis, and delay analysis. To detect HTs, most methods require a Trojan-free reference golden IC. A signature from these golden ICs is extracted and used to detect ICs with HTs. However, access to a golden IC is not always feasible. Thus, a mechanism for HT detection is sought that does not require the golden IC. Machine Learning (ML) approaches have emerged to be extremely useful in helping eliminate the need for a golden IC. Recent works on utilizing ML for HT detection have been shown to be promising in achieving this goal. Thus, in this tutorial, we will explain utilizing ML as a solution to the challenge of HT detection. Additionally, we will describe the Electronic Design Automation (EDA) tool flow for automating ML-assisted HT detection. Moreover, to further discuss the benefits of ML-assisted HT detection solutions, we will demonstrate a Neural Network (NN)-assisted timing profiling method for HT detection. Finally, we will discuss the shortcomings and open challenges of ML-assisted HT detection methods.

2. Gotcha! I Know What You are Doing on the FPGA Cloud: Fingerprinting Co-Located Cloud FPGA Accelerators via Measuring Communication Links

   Chongzhou Fang, Ning Miao, Han Wang, and 5 more authors

   Apr 2023

2022

1. Survey of Machine Learning for Electronic Design Automation

   Kevin Immanuel Gubbi, Sayed Aresh Beheshti-Shirazi, Tyler Sheaves, and 5 more authors

   In Proceedings of the Great Lakes Symposium on VLSI 2022, Apr 2022

   Abs

   An increase in demand for semiconductor ICs, recent advancements in machine learning, and the slowing down of Moore’s law have all contributed to the increased interest in using Machine Learning (ML) to enhance Electronic Design Automation (EDA) and Computer-Aided Design (CAD) tools and processes. This paper provides a comprehensive survey of available EDA and CAD tools, methods, processes, and techniques for Integrated Circuits (ICs) that use machine learning algorithms. The ML-based EDA/CAD tools are classified based on the IC design steps. They are utilized in Synthesis, Physical Design (Floorplanning, Placement, Clock Tree Synthesis, Routing), IR drop analysis, Static Timing Analysis (STA), Design for Test (DFT), Power Delivery Network analysis, and Sign-off. The current landscape of ML-based VLSI-CAD tools, current trends, and future perspectives of ML in VLSI-CAD are also discussed.

2. LOCK&ROLL: Deep-Learning Power Side-Channel Attack Mitigation Using Emerging Reconfigurable Devices and Logic Locking

   Gaurav Kolhe, Tyler Sheaves, Kevin Immanuel Gubbi, and 5 more authors

   In Proceedings of the 59th ACM/IEEE Design Automation Conference, Apr 2022

   Abs

   The security and trustworthiness of ICs are exacerbated by the modern globalized semiconductor business model. This model involves many steps performed at multiple locations by different providers and integrates various Intellectual Properties (IPs) from several vendors for faster time-to-market and cheaper fabrication costs. Many existing works have focused on mitigating the well-known SAT attack and its derivatives. Power Side-Channel Attacks (PSCAs) can retrieve the sensitive contents of the IP and can be leveraged to find the key to unlock the obfuscated circuit without simulating powerful SAT attacks. To mitigate P-SCA and SAT-attack together, we propose a multi-layer defense mechanism called LOCK&ROLL: Deep-Learning Power Side-Channel Attack Mitigation using Emerging Reconfigurable Devices and Logic Locking. LOCK&ROLL utilizes our proposed Magnetic Random-Access Memory (MRAM)-based Look Up Table called Symmetrical MRAM-LUT (SyM-LUT). Our simulation results using 45nm technology demonstrate that the SyM-LUT incurs a small overhead compared to traditional Static Random Access Memory LUT (SRAM-LUT). Additionally, SyM-LUT has a standby energy consumption of 20aJ while consuming 33fJ and 4.6fJ for write and read operations, respectively. LOCK&ROLL is resilient against various attacks such as SAT-attacks, removal attack, scan and shift attacks, and P-SCA.

3. Breaking the Design and Security Trade-off of Look-up-Table–based Obfuscation

   Gaurav Kolhe, Tyler David Sheaves, Sai Manoj P. D., and 4 more authors

   ACM Trans. Des. Autom. Electron. Syst., Jun 2022

   Abs

   Logic locking and Integrated Circuit (IC) camouflaging are the most prevalent protection schemes that can thwart most hardware security threats. However, the state-of-the-art attacks, including Boolean Satisfiability (SAT) and approximation-based attacks, question the efficacy of the existing defense schemes. Recent obfuscation schemes have employed reconfigurable logic to secure designs against various hardware security threats. However, they have focused on specific design elements such as SAT hardness. Despite meeting the focused criterion such as security, obfuscation incurs additional overheads, which are not evaluated in the present works. This work provides an extensive analysis of Look-up-table (LUT)–based obfuscation by exploring several factors such as LUT technology, size, number of LUTs, and replacement strategy as they have a substantial influence on Power-Performance-Area (PPA) and Security (PPA/S) of the design. We show that using large LUT makes LUT-based obfuscation resilient to hardware security threats. However, it also results in enormous design overheads beyond practical limits.To make the reconfigurable logic obfuscation efficient in terms of design overheads, this work proposes a novel LUT architecture where the security provided by the proposed primitive is superior to that of the traditional LUT-based obfuscation. Moreover, we leverage the security-driven design flow, which uses off-the-shelf industrial EDA tools to mitigate the design overheads further while being non-disruptive to the current industrial physical design flow. We empirically evaluate the security of the LUTs against state-of-the-art obfuscation techniques in terms of design overheads and SAT-attack resiliency. Our findings show that the proposed primitive significantly reduces both area and power by a factor of 8 ( times ) and 2 ( times ) , respectively, without compromising security.

4. Silicon Validation of LUT-Based Logic-Locked IP Cores

   Gaurav Kolhe, Tyler Sheaves, Kevin Immanuel Gubbi, and 6 more authors

   In Proceedings of the 59th ACM/IEEE Design Automation Conference, Jun 2022

   Abs

   Modern semiconductor manufacturing often leverages a fabless model in which design and fabrication are partitioned. This has led to a large body of work attempting to secure designs sent to an untrusted third party through obfuscation methods. On the other hand, efficient de-obfuscation attacks have been proposed, such as Boolean Satisfiability attacks (SAT attacks). However, there is a lack of frameworks to validate the security and functionality of obfuscated designs. Additionally, unconventional obfuscated design flows, which vary from one obfuscation to another, have been key impending factors in realizing logic locking as a mainstream approach for securing designs. In this work, we address these two issues for Lookup Table-based obfuscation. We study both Volatile and Non-volatile versions of LUT-based obfuscation and develop a framework to validate SAT runtime using machine learning. We can achieve unparallel SAT-resiliency using LUT-based obfuscation while incurring 7% area and less than 1% power overheads. Following this, we discuss and implement a validation flow for obfuscated designs. We then fabricate a chip consisting of several benchmark designs and a RISC-V CPU in TSMC 65nm for post functionality validation. We show that the design flow and SAT-runtime validation can easily integrate LUT-based obfuscation into existing CAD tools while adding minimal verification overhead. Finally, we justify SAT-resilient LUT-based obfuscation as a promising candidate for securing designs.

5. Neuromorphic-Enabled Security for IoT

   Soheil Salehi, Tyler Sheaves, Kevin Immanuel Gubbi, and 6 more authors

   In 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS), Jun 2022

2021

1. Securing Hardware via Dynamic Obfuscation Utilizing Reconfigurable Interconnect and Logic Blocks

   Gaurav Kolhe, Soheil Salehi, Tyler David Sheaves, and 4 more authors

   In 2021 58th ACM/IEEE Design Automation Conference (DAC), Jun 2021

2019

1. Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality

   Gaurav Kolhe, Hadi Mardani Kamali, Miklesh Naicker, and 6 more authors

   In 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Jun 2019

2018

1. Static Design of Spin Transfer Torques Magnetic Look Up Tables for ASIC Designs

   Aliyar Attaran, Tyler David Sheaves, Praveen Kumar Mugula, and 1 more author

   In Proceedings of the 2018 on Great Lakes Symposium on VLSI, Jun 2018

   Abs

   In this paper, we propose a static approach to the design of Spin Transfer Torque Look Up Tables (STT-LUT) for integration in ASIC and investigate the sensing reliability in the proposed design in detail. The proposed design style utilizes STT-Latches that their sensing reliability is key in determining the overall reliability of the proposed static STT-LUT. The simulation results in a 10nm FinFET CMOS technology shows that the proposed static STT-LUT design exhibits up to 26% read delay reduction compared to the best dynamic STT-LUT design, and more than 2.5X reduction in sensing failure rate.